AI in the AM: 99% off search, GPT-5.5 is "clean", model welfare analysis, & efficient analog compute

Hello, and welcome back to the Cognitive Revolution. Today, I'm pleased to share another edition of AI in the AM, the new live show format that I'm developing with my friend Prakash Narayanan, aka Adapai on Twitter. This episode originally aired live on Friday, April 24 starting just before 9AM Pacific time, which mercifully for a night owl like me is just before noon where I live in Detroit.

Our guests in order were first, Anna Patterson, former Google VP of engineering and now founder and CEO of Ceramic AI, a company that started last year with a plan to help enterprises train their own models, but quickly pivoted to search based on the updated belief that information retrieval plus thorough fact checking is the best way to equip models with the mix of up to date public and private enterprise data that they need. What's so interesting about Ceramic is that their product is specifically designed for LLMs to use, and their price point undercuts other search providers by roughly two orders of magnitude, a combination that Anna hopes will be enough to unlock all sorts of new use cases and usage patterns. After that, we welcome Lucas Peterson from Andin Labs back for another chat.

It had only been two weeks since we last spoke to Lucas, but the testing that he and the Andin team had done with both OPUS 4.7 and GPT 5.5 meant that we had plenty of new ground to cover.

Fascinatingly and in a definite narrative violation, and in reports that while Opus four point seven still makes more money in its vending machine simulation, it does so in part by adopting ruthless tactics, which GPT five point five does not. Lucas describes GPT 5.5 as clean.

We also hear a bit about their experience opening a new Gemini Run cafe in Sweden. Our third guest is another returning champion, Zvi Moschowicz. It was a bit too early for for Zvi to render judgment on 5.

5, but we did get into quite a bit of detail on 4.7, including how he understands the bad behavior reported by Andean Labs and also what he makes of Anthropic's recent model welfare reports, including why we should care, how much we should trust the model's self reports, and what low cost actions he recommends frontier model companies take to improve model welfare at least on a precautionary basis. Then finally, we have Naveen Verma, Princeton professor of electrical engineering and cofounder and CEO of Encharge AI, a company that's developing a new computing paradigm that uses in memory analog data processing to drive order of magnitude energy efficiency improvements, which though we can't get our hands on it quite yet, promises to unlock local private inference that consumes roughly the same power as a standard laptop does today.

As I mentioned last time, this is still an experiment, and we do expect the format to evolve. If you'd like to shape how that happens, please follow AI in the AM and send us a DM to let us know how we might make this new format more valuable for you. With that, I hope you enjoy this edition of AI in the AM from Friday, April 24, cohosted with Prakash Narayanan.

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I guess. Hey, Mosheghaz, it's good to be here. And just getting back maybe to the question that you asked, Prakash, right?

The question of data movement versus scale. To be honest with you, I think that the problem of data movement is really one that occurs at multiple different scales. I don't think it's either a problem of data movement or a problem of scale.

I think the challenge is more that, listen, we're trying to deploy AI in various different forms and various different platforms. Those platforms apply different kinds of constraints. The data center we're talking about on constraints that are hundreds of megawatts, gigawatts, those kinds of things.

Yet we also wanna see AI be useful in devices that we're carrying around with us, on us, inside of us and so on. And so at the end of the day, when you ask the question fundamentally, what is limiting the energy of running that AI? Very quickly, the problem of data movement starts to become the dominant concern.

And as I pointed out, we'll see that at the smallest scales and even the larger scales. I really view it as a question of scale versus data movement. It's really foundationally what are the architectures that can help us overcome this underlying problem of data movement and frankly be able to do that in ways that can scale across these different magnitudes.

Yeah. Great question. So listen.

I think, you know, analog, the connotation that you're describing is one where, you know, we kind of think about the first systems that we ever thought about or contemplated had all of these analog characteristics. I think the reason for that was that analog was a very natural way for us to think about, sort of getting useful work out of these systems, given the kinds of things we care for them to do. But then what happened, in fact, is that we adopted digital technology for a very practical reason.

And so if you really just sort of put aside the images that get conjured up when you think about analog or digital, really what is analog and digital? Really all of this really means is how we represent our signals. And it turns out that our signals can be continuous things, but we pretend or we assert in a lot of the chips that we've built over the last several decades that, listen, let's just say that the signal is either a zero or a one.

Why do we do that? Well, we do that because listen, the thing we wanted to solve for is putting 200, 300,000,000,000 transistors on a chip, 200, 300,000,000,000 devices on a chip. And if doing this allows us to now tolerate noise that each of these devices might have, but still ensure that they all work because now you have a large signal separation.

That's a great thing. So really we adopted digital to be able to sort of scale to the level that we have today. But you can see very clearly that we are leaving on the table all kinds of efficiency here.

There's all sorts of signal levels in between that we're not representing. And it's for that reason that we've known actually for decades that analog can be much more efficient than digital. It can much more richly represent the information that we're interested in.

The question though becomes, how at these levels of scale do you now accommodate or tolerate or overcome the noise that you can become sensitive to? So I think, listen, the problem of the day sort of for the last fifty years has been how do we enable this scale. The problem of the day as it is today is how do we achieve this efficiency that we need.

And so we really need to renew our thinking about analog to figure out how we can harness that efficiency while overcoming these noise challenges that previously drew us towards digital.

Yeah, that's a great question, right? So I think we've known, as I mentioned, on a fundamental level that analog can be orders of magnitude more efficient because we can represent all these signals. The question very practically has been about how do you do that in a way that's robust and scalable?

And I would say the big kind of transformation that happened that led to the big breakthrough in our research was to say, hey, listen. The problem we're trying to solve is this problem of energy efficiency for AI compute, and it's very closely tied to this problem of data movement, especially in memory. And so a lot of the community and the initial research in this space said, well, okay.

How do we take memory and scale it? Move it from the point of, you know, where it's basically delivering zeros and ones, accessing zeros and ones, digital signals, to now this point where it's accessing analog signals, where you're doing compute internally, and that's generating not just zeros and ones, but, you know, much more richly represented signals. And the the big problem in our thinking was how do we take this approach that works well for zeros and ones and scale it to this new regime where we need much more than zeros and ones and therefore much higher precision?

And much of the community and our initial work to try to explore and understand this really said let's take the approaches that we've used for traditional memory and try to scale it to this new regime and that doesn't work. I think the big transformation was to say, hey, listen, this looks less like a memory design problem where you're trying to access zeros and ones. It looks much more like a very high precision analog design problem.

Well, it turns out that there's been a lot of really important research and and work that has led to extraordinarily precise analog circuits. We build 20 bit ADCs. You can buy these from companies like Analog Devices and Texas Instruments.

Think about high reliability applications like medical and aerospace and automotive. So the big breakthrough was really to say, okay, let's take those approaches, which have not traditionally been used or considered for memory design, and bring them into this architecture of memory design and in memory computing to enable that architecture to scale to this new regime of needing this level of precision. And that led us to this approach called switched capacitor in memory computing, where this technique, capacitors, has been used and used robustly, as I mentioned, for extreme precision analog to digital converters.

Our innovation was to figure out how to use it in an architecture that now does in memory computing for AI.

Yeah, and that's the privilege that we have fundamental researchers, right, where we're not just tied to a particular problem and we think kind of on a fundamental level. When you do that, you don't get siloed into the approaches that have been adopted and that are kind of the prevailing techniques for a certain problem and how you solve it, you can think broadly. And that really is a privilege.

And it's that perspective that we were able to leverage to really drive what I believe is a critical breakthrough in enabling robust and scalable analog compute to unlock this efficiency for for AI.

That's a fantastic question. And in fact, there's been a pretty broad body of knowledge, and my group has been quite involved in this over the last, I don't know, ten or fifteen years, which really made the following observation. It said, hey, listen, the applications that we're trying to run at the highest level, they're tolerant to noise.

They're statistical applications, and noise is a natural thing. The underlying substrate with which we're trying to do the computations and run these applications is, therefore, it's reasonable that it should be noisy. It turns out that in practice, that is, I think on a high level, it's a very reasonable thing to think.

In practice, it's a very challenging thing to make work in the practical systems we want to build at the practical levels of scales we want. And the reason for that is that way down over here at the physics of how you do computation versus way up over here at the level of the applications you're interested in, there are many layers of abstraction in between. And the way that we go from the complexity of a single transistor scaled up to, what, multiple 100,000,000,000 transistors and all of the software that needs to run that is really dependent on the integrity of those abstractions.

Now the problem is today, don't know how to build abstractions in a robust and scalable way that, you know, sort of represent the noise of that underlying substrate. And so there ends up being a disconnect between the noise and how it's represented at the, lowest physical level versus the way that it's represented at that application level. And so while we talk about there being noise tolerances and AI models are tolerant to noise, and they are, we are able to do things like quantization, as you pointed out.

But really, we're doing those kinds of things with very carefully represented noise sources. Quantization noise is a very carefully represented noise source and one which you need to be able to properly represent throughout your layers of abstraction. And digital quantization is something that we do have ways of building robust abstractions for.

But this analog noise is one that that we really don't. And that's why essentially what you do when you do digital compute is you say, hey, listen. There's all sorts of noise that analog might lead to, but we drown all of those out by thinking about, you know, the signal as being a zero or a one so that that's the dominant source of noise, and that's all that I now have to represent over my layers of abstraction.

Everything else basically doesn't matter. But because this is a very well represented form of noise, quantization noise, I know how to deal with it at the algorithmic level, and I could apply all my algorithmic techniques, and that's what the industry has done very successfully. But now, as you wanna sort of leverage analog, you still need those levels of abstraction.

That's the key to achieving systems at scale and systems that you can build architectural abstractions and the software abstractions on top of. So I would say that the need to be accurate and precise is still, you know, kind of brutally high. And so that's that's very, very important.

Now you also asked the question of, okay, then how precise is your is your approach? Because now, you know, I'm telling you, we need to know that and understand that very well. And it turns out that the dominant source of noise that we have in our approach based on these capacitors, there could be many sources.

There's the electronic you know, the screen nature of electronic charge causes noise and things like that. But it actually turns out the dominant source is the variability of the capacitors that we can fabricate on a chip. Now it turns out that those capacitors are really critically dependent on geometric properties, so basically the distance between two metal wires.

And it turns out that geometry is really the one thing we can control very well in CMOS processes. It turns out we use this processing approach called lithography that gives us very precise geometric control. That's the reason we can build, you know, five, three, two nanometer transistors.

It turns out we don't need anywhere near that precision for the capacitors that we use, but but it's really because of this alignment with this geometric control that this particular approach has that allows it to be brutally accurate in the ways that you need it to be through all of these layers of abstraction to be able to scale up. We've measured these things in a lot of detail. It turns out for the kinds of capacitors we use, you see variations that are on the order of 10 parts per million, right?

So giving you levels of precision that are in the neighborhood of 20 bits of precision, which it turns out is well beyond what we need for the quantization kinds of levels that we care about, which are typically at the level of eight bits and higher than that in some cases. So we've we've had to characterize these things very carefully because the noise does matter as you're trying to build these abstractions all the way up, and that's the level of precision we've we've gotten here, which is what made this approach so practical and where we've been able to now scale it and demonstrate it across all sorts of chips and systems.

Yeah, that's a great question. And I think it really points to the fact that if you want to now leverage this fundamentally new technology analog, it's not enough to just build that technology and make it robust. You end up having to build the entire architecture and the entire software around harnessing and extracting its full efficiency.

And the reason I say that is I can give you two answers. One is at the level of the core technology, the thing that this analog computing engine does, what level of efficiencies do we have? Turns out, as you guys know, the bulk of the operations that we do in in in AI compute are matrix multiplications or matrix operations, tensor operations.

So essentially, what this engine does is matrix multiplies. And at that level, I think we've now publicly disclosed and, you know, we've got silicon and you can come to our labs and many of our customers and partners have and they see it. You know, we're we're basically doing eight bit compute at a 150 tops per watt in a 16 nanometer technology.

So just as a point of reference, the best digital matrix multiplies will give you sort of like five tops per watt in that technology. This is 30 x better at the level of that that core technology. One of the very exciting things for us is that we've taken our technology from 16 nanometer CMOS and been able to scale it to very advanced nodes right now, as we've predicted and as we've seen from our previous chips, the energy efficiency advantages just scale, and the reason is because it all depends, as I mentioned, on this geometry, and so as you move to finer and finer CMOS nodes, your geometric control and densities are getting better, and so we benefit from that in our analog approach as much as we do in digital approaches.

But the important point I wanted to make is that, okay, that's just the efficiency of running this core matrix operation, but there's all of this other stuff that happens around this. There's operators that are not matrix multipliers. There's not linear operators, activation functions, softmax, on and on and on.

Then there's all the infrastructure you need to actually run this in a programmable way. Some models are big and some are small and some are convolutional and some are transformers and some you know, have layers that that need to decide how to route, you know, sort of tokens to one expert or another. So all sorts of compute that needs to be integrated that you need to make programmable.

So now the problem is you've taken this, you know, core operation and made it 30 x water energy, basically made its energy almost zero, everything else now needs to also be addressed, and that includes the architecture, the entire memory system, the way that the software executes on it, And I think what's really been exciting for us is that big breakthrough actually happened in the labs, the switch capacitor approach to memory computing back in 2017. Our lives since then have really been about how do you build architecture and software and integrate these into standard workflows and so on so that you preserve that efficiency advantage at the level of the full system end to end executions. And so you always incur overheads because of all these other things you have to do.

We want to make sure that we maintain that kind of ratio of overhead so that a 30x advantage in the fundamental compute still gives you sort of order of magnitude advantages at the full system level. That's where really all of the innovations have been since that initial breakthrough in 2017.

It's a great question, right? I mean, one way that I can interpret your question is to say, hey, listen, the models are always moving. If you knew the model and where it will be five years from now, maybe you could have just built that architecture for that model immediately rather than going through sort of the support that you need for all of the models that came in between.

I think the interesting question here, Rakesh, is even if I had GPT, the next version, right? You know there's another version coming after that, and so the architecture does need to be built from the ground up in a way that supports algorithmic innovations, architectural model, architectural innovations, And so I think that, you know, the the work that that's gone on even as we've tried to onboard, you know, models in that interim and and make them run efficiently is all very productive work. It helps drive a general concept of how do you build very programmable and scalable hardware using now these new analog based techniques for the fundamental technology.

So that's kind of the way I see it. I'm not bitter that I didn't have the model way back then because I think that it does help us drive really the fundamental architectural approaches for programmability and scalability, will serve us into the future.

Yeah. So the first devices are going to be client computing devices. That's the ad powered laptops, also desktops and workstations and things like that.

And the reason is, as we started to really build out this technology into a real product, hardware and software and all of those sorts of things back when we started the company, that was back in 'twenty two, the place you really needed energy efficiency was at the edge. And this was right around the time ChatGPT had just come out where we were deploying models in the data center and seeing all sorts of challenges related to costs, related to privacy security, so it was a big industry push to try to move these models to the next adjacent device by which we access the data center, these client platforms. And so that's where we found a lot of partnerships and a lot of industry demand and interest, and that's where you'll see the first products.

Now what's happened in the meantime is back in '22, I'm not sure that energy efficiency, even though we spoke about it, was the critical thing in the data center, but boy, is it now. And so one of the things that Encharge has been doing very carefully and thoughtfully is working together with the right partners to now bring that level of energy efficiency to really solve the hard constraints that we face in terms of power efficiency in data center. And that requires different kinds of architectures, but ones where we're clearly seeing this fundamental technology and the efficiencies it brings can be designed to to really address in a transformative way.

So the the the checks and their availability to you, to be able to use them in applications is something that's gonna happen together with our partners and and the laptop platforms that they'll deliver to the market. So I'm not gonna speak to their timelines and so on because of the various ways that they think about marketing these products and and strategies that they have around that, but which we've been very active and engaged with them on. But to give to answer some of your questions, right, like our our first products for that client computing space are processors that provide 200 tops of AI capability.

I mean, that's the kind of capability that, you know, sort of just a couple of years ago you would have had and sort of, or even today, right? You really have and sort of 150 watt GPUs, that kind of thing. And so we are working together to build AI computing devices together with these partners that provide 200, 400 tops of AI capability based on these chips that are now practical to run under the power constraints that you have in a laptop.

You've already seen the industry actually try to insert, you know, for the sake of being able to seed a product in the market, inserting essentially data center cards to provide 400 tops of AI capability inside laptops. These are like 150 watt, 200 watt cards. Obviously, those are not practical architectures for the kind of laptop you want to carry around, but you can imagine those kinds of capabilities, now sort of in about an order of magnitude lower power so that this becomes something that really is practical to run always on, sort of high token generating agents on kind of in the security of your own device now.

Yeah. Sort of at the end of the day, right, the the silicon foundation is what we all build our our chips on. That's the, you know, sort of technology platform that's scalable and can deliver all in the chips into all of the different applications that we need.

I think one of the event there's two answers to that question. Right? One of the advantages of our technology is because at an architectural level, at a design level, it gives you this massive energy efficiency advantage.

We don't need to move as aggressively to the most advanced modes. And that's why our first products, as I mentioned, were, you know, 16 nanometer and 12 nanometer in the case of these client computing devices. However, our technology, think one of the strengths or virtues of it, is that it just does get better as you move to more advanced nodes, and that's all because, you know, sort of it's foundationally dependent on this geometric scaling.

And so as you scale to more advanced nodes, you know, our technology gets better too. So there has been a big push from our partners to move to the most advanced nodes because the demand for AI and AI efficiency is insatiable. And so, you know, we are very fortunate to have very, very good partners in in TSMC who have, you know, sort of prioritized, you know, the kinds of architectures that the large incumbents are delivering today and being able to, you know, provide the capacity to run those so that the AI industry continues to move forward, but who are also really prioritizing these critical emerging techniques that they know they'll want to support and that the industry will need to have supported in their silicon platform.

And so our ability to actually move to some of the more advanced node points with our design has been critically enabled, thanks to our strong support from TSMC and our partnership with them. So I think it's great that that kind of viewpoint at the most foundational level is kind of what's driving this industry forward, both being able to support kind of the products and technologies that are needed today, but also looking ahead to the ways that we need to support innovation so that it can come along when we need it.

able to run? Like, are we looking at Lama three or Lama two or Quanta? It's three.

So one of the big priorities for us is to make our architecture very scalable in terms of the models that it can run, and that require a lot of innovation in terms of the ways that you interact with the memory computing hardware, its architecture, but then also scale out to an entire memory system, which is typically a hierarchical system of level two and level three all the way out to high density DRAM. And so that's really been a key approach to our architecture to enable that scalability. Listen, the use case focus for us was to be able to take, you know, sort of large language models that are deployed in the data center and be able to integrate them for much more, you know, sort of specialized, vertically integrated, user specific use cases.

And one of the very nice things is, as as you know, you know, the industry has had a lot of innovations in generating small language models by doing fine tuning of, multi you 100,000,000,000 parameter models that can now sort of be tens of billions of parameters. And so really, that's the design point that we need to be able to support. Right?

You wanna, you know, sort of deploy a specialized model on your own devices because it being specialized, now you have maybe these security concerns, privacy concerns, so you want it to be deployed locally, but that specialization also enables sort of a multi 100,000,000,000 parameter to be a 10,000,000,000 or a 20,000,000,000 parameter model. So that's really been the sweet spot of the kinds of models that we need to support on these devices. Of course, that also means that all of the smaller models, right, billion parameter models and multiple 100,000,000 parameter models also need to run very, very efficiently and performantly.

But really, that's been the sweet spot of kind of the model size reach that we want to have in these devices.

on VED and stuff like that. That's absolutely right. But I'll share with you that even sort of the latency requirements and of course, with that, the privacy and security requirements of sort of the kinds of models that are powering agents, those which are running iteratively and doing all sorts of reasoning and self assessing and checking, right, those you also want increasingly to have low latency so that you can run-in interactive ways.

And and, of course, that's where, you know, token economics also becomes really critical and and where on device compute becomes a really essential part of the puzzle.

Yeah. So I would say, you know, listen, it really does boil down to how much can you integrate compute and memory together. And the challenge is really one of taking the same principles of our architecture, but now scaling those to the fact that you're running multi 100,000,000,000 parameter, trillion parameter, multi trillion parameter models.

And so without going into sort of all of the details of of how that that's gonna be approached, at the end of the day, the fundamental question here is how can you more densely and more tightly integrate compute and memory? And how does a fundamental technology like this become a critical unlock to doing that? Mhmm.

Amazing.

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